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Micrel
MICRF506BML/YML
Charge Pump
A6..A0 D7 D6
0000010 CP_HI SC_by
D5
‘0’
D4
PA_by
D3
OUTS3
D2
OUTS2
D1
OUTS1
D0
OUTS1
Table 9 shows three different loop filters, the two first
for VCO modulation and the last one for modulation
using the internal dividers. The component values
are calculated with RF frequency = 434MHz, VCO
The charge pump current can be set to either 125 μ A
or 500 μ A by CP_HI (‘1’ → 500 μ A). This will affect
the loop filter component values, see “PLL Filter”
section. In most cases, the low current is best suited.
For applications using phase detector frequency and
gain = 32MHz/V and charge pump current = 125 μ A.
Other settings are shown in the table. The varactor
pin capacitance (pin 29) of 5pF does not influence
on the component values for the two filters with
lowest bandwidth.
high PLL bandwidth, the 500 μ A can be a better
choice.
PLL Filter
VCO
Baud Rate
(kbaud/sec)
>38.4
PLL
BW
(kHz)
0.8
Phase
Margin( ? )
56
Phase
Detector
Freq.
(kHz)
100
C1
10nF
C2 R1
100nF 6.2k ?
R2
0
C3
NC
The design of the PLL filter will strongly affect the
performance of the frequency synthesizer. The PLL
VCO
Divider
>125
<20
3,2
13
56
86
100
500
680pF
150pF
6.8nF
10nF
22k ?
18k ?
0
82k ?
NC
4.7pF
filter is kept externally for flexibility. Input parameters
when designing the loop filter for the MICRF506 are
mainly the modulation method and the bit rate.
Table 9. Loop Filter Components Values
These choices will also affect the switching time and
phase noise.
Lock Detect
A6..A0 D7
D6
D5
D4
D3
D2
D1
D0
The frequency modulation can be done in two
0000001
Modulation1
Modulation0
‘0’
‘0’
RSSI_en
LD_en
PF_FC1
PF_FC0
different ways with the MICRF506, either by VCO
modulation or by modulation with the internal
dividers (see chapter Frequency modulation for
further details). In the first case, the PLL needs to
lock on a new carrier frequency for every new data
A lock detector can be enabled by setting LD_en
= 1. When pin LD is high, it indicates that the
PLL is in lock.
bit. Now the PLL bandwidth needs to be adequately
high. It is recommended to use a third order filter to
suppress the phase detector frequency, as this is
not suppressed as much as when doing modulation
Modes of Operation
A6..A0 D7 D6 D5
0000000 LNA_by PA2 PA1
D4
PA0
D3
Sync_en
D2
Mode1
D1
Mode0
D0
Load_en
on the VCO with a lower bandwidth filter.
A schematic for a second (R2=0 and C3=NC) and
third order loop filter is shown in Figure 8.
Mode1
0
0
1
Mode0
0
1
0
State
Power down
Standby
Receive
Comments
Keeps register configuration
Only crystal oscillator running
Full receive
Pin 27
Pin 29
1
1
Transmit
Full transmit ex PA state
CP_OUT
C1
C2
R2
C3
VARIN
R1
Figure 8. Second and Third Order Loop Filter
July 2006
18
M9999-092904
+1 408-944-0800
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